The significance of voltage protection circuit for input buffer is discussed with reference to a differential receiver circuit. Herein, the voltage protection circuit is a circuit between the I/O pad of an integrated circuit and a differential receiver, the protection circuit producing a signal that is used as an attenuation free input signal for the differential receiver circuit. For a differential receiver operating on 3.3V technology having common mode input range equal to 0.8V to 2.5V and having differential input sensitivity equal to 200 mV, it is essential that both the inputs of the differential receiver are free of any amplitude attenuation in common mode input range. To make the differential receiver five-volt tolerant, the input voltage must be equal to the supply voltage. Stated differently, the input voltage must exceed and cross the supply voltage.
Conventionally, NMOS transistors are used in voltage tolerant protection circuits, wherein the gate of the NMOS transistor is connected to the supply voltage. The source is connected to the Pad and the drain is connected to the Input Buffer. If the voltage at Pad is less than or equal to VDD−Vt (NMOS Threshold), the signal at the input buffer follows the Pad voltage without any amplitude attenuation. When Pad voltage is higher than the NMOS threshold then the signal at the input buffer is attenuated at NMOS threshold. For minimum allowed supply voltage, the signal at the input buffer goes beyond NMOS threshold and for large common mode input range the value of NMOS threshold may lie between the common mode input range, thus resulting in signal degradation. Further, delay is introduced on the rising edge of the signal at the input buffer for high frequency operation of the input buffer.
FIG. 1 illustrates a prior art voltage protection circuit as per US Patent Application Publication No. 2004/0007712 A1, which is hereby incorporated by reference in its entirety. Here, NMOS transistors are used for protection. As per the given circuit, VOUT follows the Pad voltage from 0V to VDD−vt (PMOS threshold), and supply voltage (VDD) is outputted at VOUT whenever input voltage crosses the PMOS threshold. There is static consumption on the supply voltage through transistors 224 & 226 when Pad voltage is less than VDD−vt (PMOS threshold) and it is undesirable to have a direct path between power supply and ground in normal operating condition. When Pad voltage is greater than VDD−vt (PMOS threshold), and 3.3V transistors are used in the protection circuit, there can be electrical stress on PMOS 234. Electrical stress on the transistors in the protection circuit is undesirable and often results in the output signal attenuation.
Accordingly what is needed is a method and system to overcome the problems encountered in the prior art voltage protection circuits and to provide a voltage tolerant protection circuit for an input buffer that prevents stress on transistors, minimizes power supply consumption and transfers signals without any change in the amplitude.